Method for synchronizing computer clocks in networks used for information transmission, device for carrying out said method and data packet suitable for the synchronization of computer clocks

ABSTRACT

The invention relates to a method for synchronizing computer clocks in networks used for the transmission of information according to which information is dispatched with a time stamp when being dispatched and which is re-transmitted with a time stamp in a confirmation of receipt. The time stamps are inserted in the outgoing or arriving data packet by a clock module ( 8 ) mounted downstream of a network controller ( 4, 10 ) once said network controller has authorized transmission. A CPU ( 2 ) generates actuator signals that are provided with an identifier and that correct the clock modules ( 8 ) on the basis of a comparison between the time stamps in a confirmation of receipt of the addressee of the information and the time stamp of the corresponding transmitted information.

The invention relates to a method for synchronizing computer clocks innetworks for the information transfer, in which a data packet is sentwith a time stamp at the moment of its sending, and is returned with atime stamp in a receipt confirmation, a device for synchronizingcomputer clocks in networks for the information transfer, in which adata packet is equipped with a time stamp at the moment of its sending,and with a time stamp at the moment of receipt at the target address, aswell as a data packet for synchronizing computer clocks in informationtransfer networks for networked computers.

BACKGROUND OF THE INVENTION

In addition to a central processing unit (CPU) and a memory, a computeralso requires interfaces to the outside for its operation that can beconstructed in different ways. A system bus is directly connected to thecomputer, which is generally constructed as a parallel interface so thatdepending on the processor clock, or on the bus clock, a multitude ofbits can be allowed in and out. If information is to be transferred vialines, this can generally also occur via parallel interfaces, wherebythe line length is limited due to the large amount of lines required.Transfer processes were therefore developed for the distance transfer ofinformation or data, in which the initially parallel existing signalswere converted into serial signal so that they could then be sent andreceived via a low amount of lines. For this purpose, computers areusually equipped with network cards that are connected to the respectivesystem bus, whereby standard parallel interfaces were recommended inthis case. One example of such a standard interface is the so-called PCIbus. A network controller or a network card is successively connected tosuch a bus, which in addition to the network controller also contains anadditional interface that is adjusted to the selected transfer medium,or to the selected network structure. Among other tasks, thismedia-specific interface takes on the adjustment of the levels to thepost-connected line network, whereby bus networks are commonly used. Inthe case of bus networks, all computers are connected to a mutual bus,whereby each participant can access the bus, and can reach eachparticipant connected. In order to control access to such busstructures, the CSMA (carrier sense multiple access) process is used,for example. In this process, an attempt is made to avoid collisions bysimultaneously occurring transfers. If two participants simultaneouslyrecognized and sent a free line network, such collisions would occur.However, this is prevented by the fact that the transfer media is tappedby the stations before the transfer is started, for which bit structuresare used with which collision recognition is possible. Such bitstructures are called CSMAICD packets, whereby CD stands for “collisiondetection” or collision recognition. In addition to bus networks, starnetworks, ring networks, and token ring networks are common, and varioustypes of transfer protocols are used with which a more or less largemaximum transfer speed can be achieved. Such transfer protocols havebeen known, for instance, as Ethernet protocols (IEEE 803), or asfirewire protocols (IEEE1394). The analog applies to, for instance, CAN,FDDI, ATM, or gigabit Ethernet protocols.

The network controller, together with the media-specific interface,provides the translation of the parallel data flows into a serial dataflow, whereby the desired conventions, or protocols are maintained inorder to avoid any collisions. Network cards usually contain memory inorder to retain information as long as a data line is occupied, or thedata packet is incomplete, or is present in a form that is unsuitablefor the protocol. This stored information is subsequently fed into thenetwork when a free line is detected. Because of this intermediatestorage until the release of transfer, the data packets experiencevarious delays due to the network card. This is also true for so-calledswitches, in which certain information to be sent to an addressee isstored up until a certain time, at which a larger packet can be sent ata higher speed.

In computer networks that must be checked to ensure that a universaltime base is available to all computers, it is also important torecognize when the information was received from another networkedcomputer in addition to when the information was sent. Although computerclocks for the clocking of a computer allow for the determination oftime at which a processor has made information available to the networkcard, they do not recognize when the network card has actually performedthe transfer via the data transfer line. Therefore, additional computerclocks have been recommended, by means of which the time critical datapackets are equipped with a time stamp at the time of the actualtransfer. Such computer clocks have already been connected between thenetwork controller and the media-specific interface, whereby the networkcontroller and the media-specific interface are connected to each othervia a media-independent interface (MIIF), and the computer clock isconnected between these two components. In order to make completeinformation on the actual time of transfer of the information availableto the respective sending CPU, this inter-connected computer clock mustecho the time of the actual transfer to the assigned processor. In thisregard, it is advisable to perform an echo into the system bus via aseparate component group, whereby such components can be called PCIbridges, for instance, and communicate with the PCI bus of the computer.The circuit complexity and hardware expenditure of such modifications,however, is relatively high and requires the additional equipment ofcomputers with additional interfaces and additional interface cards.

DESCRIPTION OF THE INVENTION

The invention is aimed at reducing the hardware expenditure and thecircuit complexity for the synchronization of a universal time base ininformation transfer networks, and to avoid subsequent hardware changesso that the desired universal time base can be achieved at asubstantially higher precision by merely performing a respectivesoftware adjustment. In solving this task the inventive methodessentially consists of the fact that the time stamps are inserted by apost-connected clock module into the outgoing or incoming data packetafter the release of the transfer by a network controller, and that aCPU generates configuration signals for the correction of the clockmodule, said configuration signals being equipped with an identifier,wherein the generation of configuration signals is based on a comparisonof time stamps in a receipt confirmation by the addressee of the datapacket and the time stamp of the relating data packet sent. By the factthat the time stamps are inserted after release of the transfer by meansof network switching by a clock module, such clock modules can bearranged within the media-independent interface, and can also bearranged directly on the network card so that merely the respectivenetwork card must be connected to the respective system bus of theprocessor. At the same time, this arrangement ensures that the timestamp is not actually inserted until the network controller performs thetransfer. However, an echo of the correct receipt, which issimultaneously equipped with a time stamp, does not necessarily lead toa respectively active synchronization of the clock circuit as theconfiguration signals, or the setup signals, as well as possibly thecontrol signals and/or the status signals must be exchanged with theclock module for purposes of improving the precision and accuracy of thetime basis. However, such configuration signals may be sent only by theassigned CPU or a remote CPU, when an error of the time basis due toexterior influences is to be safely avoided, whereby these controlsignals may be processed only by the respectively responding clockmodule. In the controlling of all clocks by a remote CPU in the network,the data transfer of each clock to the remote CPU is achieved by meansof a simple (undocumented) return transfer of the data packet by eachlocal CPU. The required echo of status information by echoing all datapackets identified for the local computer clock to the remote computercan occur by the local CPU for the purpose of correction and control ofa local computer clock by means of a remote computer in the network.According to the invention, a CPU generates configuration signals thatare equipped with an identifier, whereby the generation of theconfiguration signals is based on a comparison of the time stampcontained in a receipt confirmation of the addressee of the data packetand the time stamp of the data packet it has sent, and provides thisexclusively to the clock module, which is to perform the respectivecorrection. Therefore, the identification additionally required in thecourse of such configuration signals ensures that the clock moduleassigned to a computer can selectively respond, and in itself cannot beinfluenced by any signals from the network so that a high degree ofsafety, as well as a higher precision provided by the possibility of acontinuous or iterative reset can be achieved.

Advantageously, the inventive method is performed in such a way thatconfiguration signals for the correction, control signals and/or statussignals of the clock modules are transferred with an identifier that isevaluated by a packet detection logic of a clock module, and that suchconfiguration signals transferred with an identifier are used for thecorrection of the time of the respective clock module. Principally, aspreviously mentioned, a separate bus connection for the echo to therelated CPU should be avoided for reasons of simplifying the expenditureof hardware. In order to ensure that the respective configurationsignals, control signals and/or status signals are actually transferredonly to the respectively assigned clock module, it is thereforenecessary to ensure that the identifiers are detected and evaluated by acomponent of the clock module itself, or the network controller.

Some media-specific interfaces, for instance, can be switched by meansof an additional data line in such a way that such signals aretransferred back not to the network, but to the CPU, which havegenerated the signals, whereby such an interface switching can also berealized directly in a component group that contains the clock circuit.Advantageously, the action chosen for this purpose is that the networkcontroller communicates directly with an interface circuit and generatesa command for causing configuration, control, and/or status signals thatare sent to the clock circuit by a CPU to return to the CPU that hasgenerated the signals.

In this regard it is principally possible and of benefit to use aspecial processor, i.e. a remote CPU, for the synchronization, wherebythe action advantageously chosen for this purpose is that the datapackets for the correction, control, and status signals of a localcomputer clock are calculated on a remote computer in the network, andare sent out as a data packet to the network controller of therespective computer clock.

In an especially simple manner, the synchronization of computer clocksin networks occurs by means of switches, whereby the residence time ofeach data packet in the switch is measured, and each switch is equippedwith a computer clock and suitable time measurement device at all switchports.

The inventive device for synchronizing a universal time basis isessentially characterized in that a clock module is assigned to eachnetwork controller, which contains a packet detection logic and a clockcontroller, whereby configuration, control, and/or status signals sentout by a CPU are performed, or processed after the clock controllerchecks the target address in the network controller, and information isentered into the detected packet. As previously mentioned, the detectionof the signals equipped with an identifier can be performed by acomponent of the clock module. The device can also be embodied in such away that the network controller is connected to the interface via aseparate line for the transmission device reverse, bypassing the clockmodule, in order to detect configuration, control, and/or status querysignals.

In order to additionally reduce the extent of switching-technicalmodifications, however, such a separate control line between the networkcontroller and the media-specific interface can be omitted if therespective logic for the detection of configuration, control, and/orstatus query signals and a respective interface are integrated into theclock module that is switched to the media-independent interface, whichperforms the return of such signals to the respective CPU that hasgenerated the signals. Advantageously, the embodiment is thereforechosen so that the packet detection logic for the detection ofconfiguration, control, and/or status query signals, and the relatedcomputer clock are combined into one component group, and particularlyare integrated. This creates a particularly simple circuit arrangementthat can be easily integrated into conventional network cards, in whichit is subsequently merely necessary to provide the CPU with thepossibility by means of respective software programming, to evaluate thereturning signals correspondingly in order to generate the requiredsetup signals for the post adjustment of the clock module.

The data packet for the synchronization of clock circuits in informationtransfer networks for networked computers is for this purposecharacterized that the data packet contains at least one identifier forpacket types in addition to the fields for the target address, sourceaddress, and data, which is characteristic for configuration, control,and/or status query signals. The common transfer protocols, as they areapplied in data and communication technology, usually contain a definedamount of bits for the packet type detection so that suchidentifications can be accommodated without modification, for instancein the bit structure of CSMA data packets with collision identification.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in further detail by the embodiment examplesschematically illustrated in the drawings as follows. The drawings show,in

FIGS. 1 and 2, a first and a second embodiment of inventive devicesconnected to each other, and, in

FIG. 3, a further embodiment of the inventive device.

FIG. 1 shows a device 12 comprising a clock 1 and an associated CPU 2.The CPU 2 hereby represents the central component that is connected to anetwork controller 4 of a network card via a bus structure 3 designed asa parallel bus. In the illustration according to FIGS. 1 and 2, a busstructure was selected as an example, the backbone of which isidentified by 5, which backbone 5 may connect the device 12 with anotherdevice 13 connected to the backbone 5. The connection to backbone 5 isestablished by means of the media specific interface 6, in which theadjustment to the levels required by the respective transmission mediumalso occurs. Lines 7 are provided between the interface 6 and thenetwork controller 4, which all represent a media-independent interfacebetween the network controller 4 and the media specific interface 6. Aclock module 8 is switched into these lines 7. This clock module 8equips the data packet with a time stamp in case of time criticalinformation every time when the network controller relays a data packetto the media specific interface 6. The echo that a signal has beenreceived by another CPU 2, such as the CPU 2′ of device 13, occurs viathe line 5, the media specific interface 6, the network controller 4,and the parallel bus 3 to the CPU 2. A comparison of the time stamp ofthe sending CPU's 2 clock module 8 with the time stamp of the receiverpermits a conclusion as to the accuracy of the time basis inconsideration of the known or measured run time of the signals betweentwo known addresses, and subsequently enables the CPU 2 to generatesignals with which the clock frequency of the own clock module 8 isadjusted accordingly in order to increase accuracy. Synchronizations canbe achieved in this way in which the known maximum deviation of theclocks in the clock generators of processors that are different fromeach other can be maintained within a nanosecond range. The respectivesetup or configuration signals are now relayed from the CPU 2 to theclock module 8 via the network controller 4, whereby according to theembodiment shown in FIGS. 1 and 2, the network controller 4 itself iscapable of detecting such configuration signals due to theiridentification as configuration signals. In these cases, the networkcontroller 4 communicates to the media specific interface 6 via the line9 that this information is not intended for a relay to the network 5,but instead is to be returned to its own CPU 2 together with arespective confirmation by the clock module 8 of the correctionperformed.

Thus, the synchronization of clock module 8′ of device 12 with the clockmodule 8 of device 13 happens as follows: A data packet compiled by CPU2 is forwarded to the network controller 4. After the data packet hasbeen released by the network controller 4 it passes the clock module 8,where a time stamp is inserted into the data packet. The data packet viainterface 6 and backbone 5 is then sent to device 13, where it firstpasses the interface 6′ and then receives a time stamp by clock module8′ representing the time of receipt of the data packet by device 13.Subsequently, the data packet is forwarded to the network controller 4′and to CPU 2′. After receipt of the data packet, CPU 2′ sends the datapacket or a receipt confirmation back to CPU 2 of device 12 so that CPU2 may generate a configuration signal based on a comparison between thetime stamp inserted by clock module 8 at the time of sending said datapacket and the time stamp inserted by clock module 8′ at the time ofreceiving said data packet, considering known or measured run times ofsignals between the device 12 and device 13. This configuration signalcontains time correction information for the clock module 8. Anotherconfiguration signal may be generated containing time correctioninformation for the clock module 8′ of the remote device 13 so thatclock module 8 and clock module 8′ are each corrected in order toachieve synchronization of both clock modules 8, 8′. The networkcontrollers 4, 4′ and the clock modules 8, 8′ are able to identify theirrespective configuration signals by means of identifiers contained inthe configuration signals. Upon receipt of a configuration signal by CPU2, network controller 4 communicates to the media specific interface 6via the line 9 that this configuration signal is not intended for arelay to the network 5. The configuration signal is then forwarded toclock module 8, where the time correction is performed, and thenforwarded to interface 6, which returns the configuration data packet toits own CPU 2 together with a respective confirmation by the clockmodule 8 of the correction performed.

The embodiment according to FIG. 3 shows a device 15, which is analternative embodiment of device 12 and 13, whereby the additionalcontrol line 9 is omitted. In this embodiment, the clock module 8′″ bywhich the time stamp is applied, contains an additional simple variationof a network controller 10′″ in the form of a packet detection logic anda clock controller 11′″ so that the respective identification ofconfiguration signals can occur within the component group contained inthe clock module 8′″.

FIG. 2 shows a backbone 5, to which three device 12, 13, 14 areconnected, whereby the clock modules 8′, 8″, of devices 13, 14 will besynchronized by device 12. To this end, CPU 2 of device 12 sends a datapacket to device 13 and another data packet to device 14, whereby a timestamp is inserted into each data packet by clock module 8 at the time ofsending. Clock module 8′ inserts a time stamp into the data packet sentto device 13 at the time the data packet is received by device 13 andclock module 8″ inserts a time stamp into the data packet sent to device14 at the time the data packet is received by device 14. Subsequently,the data packets are returned to device 12, whereby CPU 2 generates aconfiguration signal intended for correction of clock module 8′ based ona comparison between the time stamp inserted by clock module 8 at thetime of sending said data packet and the time stamp inserted by clockmodule 8′ at the time of receiving said data packet, considering knownor measured run times of signals between the device 12 and device 13,and a configuration signal intended for correction of clock module 8″based on a comparison between the time stamp inserted by clock module 8at the time of sending said data packet and the time stamp inserted byclock module 8″ at the time of receiving said data packet, consideringknown or measured run times of signals between the device 12 and device14, so that the clock modules 8′ and 8″ will be synchronized.

1. Method for synchronizing computer clocks in networks used forinformation transfer, comprising the steps of: sending a first datapacket from a sender to an addressee; inserting a time stamp into saiddata packet at the moment said data packet is sent by the sender;inserting a time stamp into said data packet when said data packet isreceived by the addressee, wherein said time stamps are inserted by apost-connected clock module into said data packet, after release oftransfer of the data packet by a network controller; and sending saiddata packet or a receipt confirmation back from said addressee to saidsender, wherein a CPU of the sender generates configuration signals forcorrection of one or more of a clock module of the sender and a clockmodule of the addressee, said configuration signals being equipped withan identifier, wherein said generation of configuration signals is basedon a comparison between the time stamp inserted at the time of sendingsaid data packet and the time stamp inserted at the time of receivingsaid data packet, considering known or measured run times of signalsbetween the addressee and the sender, said configuration signals beingsent to and processed by one or more of the clock modules of the senderand of the addressee, thereby achieving synchronization.
 2. Methodaccording to claim 1, wherein at least one of configuration signals forthe correction of the clock module of the sender or the addressee,control signals, and status signals of the clock modules, is transferredwith an identifier that is evaluated by a packet detection logic of oneor more of the clock modules of the sender and of the addressee, andwherein said configuration signals transferred with said identifier isused for correction of time of one or more of the clock modules of thesender and of the addressee.
 3. Method according to claim 1, wherein thenetwork controller directly communicates with an interface circuit andgenerates a command for causing at least one of configuration, controland status signals that are sent to the clock module of the sender bythe CPU of the sender to return to the CPU of the sender.
 4. Methodaccording to claim 2, wherein the network controller directlycommunicates with an interface circuit and generates a command forcausing at least one of configuration, control and status signals thatare sent to the clock module of the sender by the CPU of the sender toreturn to the CPU of the sender.
 5. Method according to claim 1, furthercomprising the step of sending back said first data packet from saidaddressee to said sender, wherein at least one of configuration,control, and status signals for a computer clock of the addressee arecalculated on the CPU of the sender, and are sent out as aconfiguration, control and status data packet to the network controllerof the computer clock of the addressee.
 6. Method according to claim 2,further comprising the step of sending back said first data packet fromsaid addressee to said sender, wherein at least one of configuration,control, and status signals for a computer clock of the addressee arecalculated on the CPU of the sender, and are sent out as aconfiguration, control and status data packet to the network controllerof the computer clock of the addressee.
 7. Method according to claim 3,further comprising the step of sending back said first data packet fromsaid addressee to said sender, wherein at least one of configuration,control, and status signals for a computer clock of the addressee arecalculated on the CPU of the sender, and are sent out as aconfiguration, control and status data packet to the network controllerof the computer clock of the addressee.
 8. Method according to claim 4,further comprising the step of sending back said first data packet fromsaid addressee to said sender, wherein at least one of configuration,control, and status signals for a computer clock of the addressee arecalculated on the CPU of the sender, and are sent out as aconfiguration, control and status data packet to the network controllerof the computer clock of the addressee.
 9. Method according to claim 1,wherein synchronization occurs via switches, whereby residence time ofsaid data packet in a switch is measured, and each switch is equippedwith a computer clock and each switch is equipped with a timemeasurement device at all switch ports.
 10. Method according to claim 2,wherein synchronization occurs via switches, whereby residence time ofsaid data packet in a switch is measured, and each switch is equippedwith a computer clock and each switch is equipped a time measurementdevice at all switch ports.
 11. Method according to claim 3, whereinsynchronization occurs via switches, whereby residence time of said datapacket in a switch is measured, and each switch is equipped with acomputer clock and each switch is equipped with a time measurementdevice at all switch ports.
 12. Method according to claim 4, whereinsynchronization occurs via switches, whereby residence time of said datapacket in a switch is measured, and each switch is equipped with acomputer clock and each switch is equipped with a time measurementdevice at all switch ports.
 13. Method according to claim 5, whereinsynchronization occurs via switches, whereby residence time of saidfirst data packet in a switch is measured, and each switch is equippedwith a computer clock and each switch is equipped with a timemeasurement device at all switch ports.
 14. Method according to claim 6,wherein synchronization occurs via switches, whereby residence time ofsaid first data packet in a switch is measured, and each switch isequipped with a computer clock and each switch is equipped with a timemeasurement device at all switch ports.
 15. Method according to claim 7,wherein synchronization occurs via switches, whereby residence time ofsaid first data packet in a switch is, and each switch is equipped witha computer clock and each switch is equipped with a time measurementdevice at all switch ports.
 16. Method according to claim 8, whereinsynchronization occurs via switches, whereby residence time of saidfirst data packet in a switch is measured, and each switch is equippedwith a computer clock and each switch is equipped with a timemeasurement device at all switch ports.
 17. Device for synchronizingcomputer clocks in networks used for information transfer, wherein datapackets are equipped with a time stamp at the moment of their sending,and with a time stamp at the moment of receipt at a target address, saiddevice comprising at least one network controller for sending andreceiving data packets, said device further comprising at least oneclock module being assigned to said at least one network controller,said clock module being post-connected to said network controller suchthat a data packet being sent is equipped with a time stamp afterrelease of transfer of said data packet by said network controller, andsaid device further comprising a CPU for generating configurationsignals for correction of the clock module, wherein said generation ofconfiguration signals is based on a comparison between the time stampinserted at the time of sending said data packet and the time stampinserted at the time of receiving said data packet, considering known ormeasured run times of signals between the network controller of thesender and the target address.
 18. Device according to claim 17, whereineach network controller comprises a packet detection logic and a clockcontroller, whereby at least one of configuration, control, and statussignals sent by said CPU are performed, or processed after the clockcontroller checks the target address in the network controller, andinformation is entered into a detected packet.
 19. Device according toclaim 17, wherein a packet detection logic for detection of at least oneof configuration, control, and status query signals, and a relatedcomputer clock, are integrated into one component group.
 20. Method forsynchronizing computer clocks in networks used for information transfer,comprising the steps of: sending a data packet from a sender to anaddressee; inserting a time stamp into said data packet at the momentsaid data packet is sent by the sender; inserting a time stamp into saiddata packet when said data packet is received by the addressee; sendingback said data packet from said addressee to said sender, wherein saidtime stamps are inserted by a post-connected clock module into said datapacket, after release of transfer of the data packet by a networkcontroller, and wherein configuration signals for correction of acomputer clock of the addressee are calculated on a CPU of the sender,and are sent out as a configuration data packet to a network controllerof a computer clock of the addressee, said configuration signals beingequipped with an identifier, wherein said generation of configurationsignals is based on a comparison between the time stamp inserted at thetime of sending said data packet and the time stamp inserted at the timeof receiving said data packet, considering known or measured run timesof signals between the addressee and the sender, said configurationsignals being sent to and processed by the computer clock of theaddressee, thereby achieving synchronization.
 21. Method forsynchronizing computer clocks in networks used for information transfer,comprising the steps of: sending a data packet from a sender to anaddressee; inserting a time stamp into said data packet at the momentsaid data packet is sent by the sender; and inserting a time stamp intosaid data packet when said data packet is received by the addressee;wherein said time stamps are inserted by a post-connected clock moduleinto said data packet, after release of transfer of the data packet by anetwork controller, and wherein synchronization occurs via switches,whereby residence time of said data packet in a switch is measured, andeach switch is equipped with a computer clock and each switch isequipped with a time measurement device at all switch ports, and whereina CPU of the sender generates configuration signals for correction ofone or more of clock modules of the sender and of the addressee, saidconfiguration signals being equipped with an identifier, wherein saidgeneration of configuration signals is based on a comparison between thetime stamp inserted at the time of sending said data packet and the timestamp inserted at the time of receiving said data packet, consideringknown or measured run times of signals between the addressee and thesender, said configuration signals being sent to and processed by one ormore of the clock modules of the sender and of the addressee, therebyachieving synchronization.